Embodiments of the present invention disclosed herein relate to a semiconductor device, and more particularly, to a nonvolatile memory device.
A nonvolatile memory device retains data even in the event that externally applied power is removed. Examples of nonvolatile memory devices include a mask ROM, an erasable programmable read-only memory (EPROM), an electrically erasable programmable read only memory (EEPROM), and the like.
FIGS. 1A, 1B, and 1C are a plan view, a sectional view taken along line I-I′ of FIG. 1A, and an equivalent circuit diagram of FIG. 1A, respectively, of a conventional EEPROM. Referring to FIGS. 1A, 1B, and 1C, a source region 12s, a drain region 12d, and a floating diffusion region 12f are formed in an active region 12 defined by a device isolation layer 13 of a semiconductor substrate 11.
A word line WL crosses over the active region 12 in a first direction of extension. A select line SL that is spaced apart from the word line WL crosses over the active region in the first direction, and is parallel to the word line WL. A bit line BL that extends in a second direction is connected to the drain region 12d by a bit line contact plug 31.
A floating gate electrode 21, an intergate dielectric layer 23, and a control gate electrode 25 is formed on the active region 12 between the drain region 12d and the floating diffusion region 12f. A gate insulation layer 15 is interposed between the floating gate electrode 21 and the active region 12. The control gate electrode 25 is connected to a word line WL. The floating diffusion region 12f extends in the active region below the word line WL. The word line WL, the drain region 12d, and the floating diffusion region 12f constitute a memory transistor MT. A portion of the gate insulation layer 15 may include an opening that exposes the active region 12. A tunnel insulation layer (not shown) having a thickness that is less than that of the gate insulation layer may be formed on the opening.
A select gate electrode 27 is formed on the active region 12 between the floating diffusion region 12f and the source region 12s. A select gate insulation layer 17 is interposed between the select gate electrode 27 and the active region 12. The select gate electrode 27 is connected to a select line SL. The select line SL, the floating diffusion region 12f, and the source region 12s constitute a select transistor ST. Unlike the memory transistor MT, the select transistor ST may include a conventional metal-oxide semiconductor (MOS) transistor structure. The select gate electrode 27 of the select transistor ST, and the floating gate electrode 21 and the control gate electrode 25 in the memory transistor MT can include a stacked structure of conductive layers, for example, that are electrically connected to each other.
In the conventional EEPROM, a memory cell unit MC includes one select transistor (ST) and one memory transistor (MT), and thus only one bit of data can be stored in each memory cell unit MC. Since the occupied active region area may be too large, this structure is not conducive to higher-integration.